module ALU3 (
  input        [7:0] A,
  input        [7:0] B,
   input        [1:0] OP ,
	  input         CLK,
  output reg   [7:0] OUT
);

wire [7:0] MUX [0:3];

assign MUX[0] = A;
assign MUX[1] = A + B;
assign MUX[2] = A - B;
assign MUX[3] = A;

always@(negedge CLK)
begin
  OUT <= MUX[OP];
end
endmodule
